Preventing Soft Errors and Hardware Trojans in RISC-V Cores.
Edian B. AnninkGerard K. RauwerdaEdwin A. HakkennesAlessandra MenicucciStefano Di MascioGianluca FuranoMarco OttaviPublished in: DFT (2022)
Keyphrases
- hardware architecture
- low cost
- multi core processors
- low power consumption
- error detection
- real time
- hardware and software
- instruction set
- hardware implementation
- application specific
- general purpose processors
- processor core
- field programmable gate array
- parallel architectures
- computing systems
- massively parallel
- processing capabilities
- error analysis
- prediction error
- level parallelism
- neural network
- parallel computation
- graphics hardware
- circuit design
- hardware design
- computer systems
- address space
- wireless sensor networks