Completeness bounds and sequentialization for model checking of interacting firmware and hardware.
Sunha AhnSharad MalikAarti GuptaPublished in: CODES+ISSS (2015)
Keyphrases
- model checking
- ibm zenterprise
- temporal logic
- computer systems
- formal verification
- model checker
- temporal properties
- automated verification
- lower bound
- finite state
- symbolic model checking
- partial order reduction
- bounded model checking
- verification method
- formal specification
- pspace complete
- epistemic logic
- reachability analysis
- timed automata
- computation tree logic
- formal methods
- finite state machines
- asynchronous circuits
- linear temporal logic
- concurrent systems
- process algebra
- transition systems
- reactive systems
- embedded systems
- game theory
- software engineering
- knowledge base
- reinforcement learning