A 5.99 TFLOPS/W Heterogeneous CIM-NPU Architecture for an Energy Efficient Floating-Point DNN Acceleration.
Wonhoon ParkJunha RyuSangjin KimSoyeon UmWooyoung JoSangyoeb KimHoi-Jun YooPublished in: ISCAS (2023)
Keyphrases
- floating point
- floating point arithmetic
- instruction set
- square root
- computer integrated manufacturing
- fixed point
- loosely coupled
- sensor networks
- sparse matrices
- wireless sensor networks
- energy efficient
- floating point unit
- higher order
- training process
- hardware implementation
- access control
- signal processing
- graphical models
- similarity measure