SEU Resilience of DES, AES and Twofish in SRAM-Based FPGA.
Uli KretzschmarArmando AstarloaJesús LázaroPublished in: ARC (2013)
Keyphrases
- power reduction
- power consumption
- low power
- low power consumption
- high speed
- field programmable gate array
- data transmission
- low cost
- gate array
- real time
- verilog hdl
- advanced encryption standard
- fpga implementation
- signal processing
- cryptographic algorithms
- parallel hardware
- random access memory
- hardware implementation
- single chip
- secret key
- hardware design
- fault tolerance
- real time image processing
- embedded systems
- software implementation
- missing data
- hardware architectures
- hardware architecture
- digital signal
- power saving
- parallel architecture
- energy consumption
- encryption algorithms
- fault tolerant
- fault model
- block cipher
- s box