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An 82-to-108GHz -181dB-FOMT ADPLL employing a DCO with split-transformer and dual-path switched-capacitor ladder and a clock-skew-sampling delta-sigma TDC.
Zhiqiang Huang
Howard Cam Luong
Published in:
ISSCC (2018)
Keyphrases
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delta sigma
high speed
user friendly
power consumption
noise shaping
shortest path
power system
transmission line
phase locked loop
fault diagnosis
analog to digital converter
image processing
wireless sensor networks
image coding
clock frequency
high voltage