An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication.
Jochen StrunkToni VolkmerWolfgang RehmHeiko SchickPublished in: DSD (2009)
Keyphrases
- high bandwidth
- low latency
- high speed
- massive scale
- low cost
- real time
- end to end
- hardware implementation
- high throughput
- highly efficient
- field programmable gate array
- high density
- data acquisition
- reconfigurable hardware
- stream processing
- virtual machine
- application specific
- communication networks
- peer to peer
- systolic array
- network traffic
- network structure
- interconnection networks
- network on chip