Glitching power reduction through supply voltage adaptation mechanism for low power array structure design.
Sangjin HongShu-Shin ChinMagesh SadasivamPublished in: ISCAS (2) (2004)
Keyphrases
- low power
- power reduction
- power consumption
- power dissipation
- low cost
- high speed
- single chip
- low power consumption
- vlsi architecture
- logic circuits
- digital signal processing
- image sensor
- power saving
- mixed signal
- gate array
- cmos technology
- energy efficiency
- nm technology
- response time
- analog to digital converter
- computer simulation
- ultra low power