An energy-efficient FPGA-based matrix multiplier.
Yiyu TanToshiyuki ImamuraPublished in: ICECS (2017)
Keyphrases
- hardware implementation
- wireless sensor networks
- floating point
- energy efficient
- singular value decomposition
- application specific
- sensor networks
- hardware design
- energy consumption
- signal processing
- multi channel
- low rank
- sensor nodes
- field programmable gate array
- linear algebra
- data gathering
- matrix representation
- maximum lifetime