Timing analysis of network on chip architectures for MP-SoC platforms.

Cristian Grecu Partha Pratim Pande André Ivanov Res Saleh

Published in: Microelectron. J. (2005)

Keyphrases

network on chip
interconnection networks
routing algorithm
network simulator
multi processor
low power
fault tolerant
message passing
data transfer
power dissipation
multistage
hardware and software
multi core processors
program execution
high speed
mobile ad hoc networks