A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems.

Pavan Poluri Ahmed Louri

Published in: IEEE Comput. Archit. Lett. (2015)

Keyphrases

network on chip
error tolerant
routing algorithm
network simulator
graph matching
data transfer
multi core processors
data mining
pattern recognition
pairwise
relational databases
sensor networks
shared memory