A 285-MHz pipelined MAP decoder in 0.18-/spl mu/m CMOS.

Seok-Jun Lee Naresh R. Shanbhag Andrew C. Singer

Published in: IEEE J. Solid State Circuits (2005)

Keyphrases

high speed
cmos technology
spl times
low power
low cost
power consumption
maximum a posteriori
nm technology
low complexity
high frequency
real time
development environment
video codec
image sensor
maximum likelihood
computational complexity
analog vlsi
successive approximation