An Optimized Implementation of AES-GCM for FPGA Acceleration Using High-Level Synthesis.
Tsubasa TakakiYang LiKazuo SakiyamaShoei NashimotoDaisuke SuzukiTakeshi SugawaraPublished in: GCCE (2020)
Keyphrases
- high level synthesis
- parallel architecture
- hardware implementation
- parallel processing
- software implementation
- high speed
- advanced encryption standard
- dedicated hardware
- image processing
- hardware design
- low cost
- field programmable gate array
- hardware architecture
- computing systems
- signal processing
- distributed systems
- higher order