An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching detector.

Ding-Guo Lin Bing-Hsun Lu Herming Chiueh

Published in: VLSI-SoC (2010)

Keyphrases

high speed
clock frequency
power consumption
low power
field programmable gate array
duty cycle
real time
genetic algorithm
relevance feedback
massively parallel
hidden markov models
detection algorithm
user feedback
high end
parallel architecture
negative selection algorithm