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A Novel Approach for Implementing Microarchitectural Verification Plans in Processor Designs.
Yoav Katz
Michal Rimon
Avi Ziv
Published in:
Haifa Verification Conference (2012)
Keyphrases
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functional verification
instruction set
plan recognition
model checking
parallel processing
plan generation
single chip
formal verification
high speed
partially ordered
efficient implementation
memory management
plan execution
distributed memory
planning problems
single processor
industry standard
low cost