A Low-Power 4-PAM Transceiver Using a Dual-Sampling Technique for Heterogeneous Latency-Sensitive Network-on-Chip.
Gyung-Su ByunMir Mohammad NavidiPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2015)
Keyphrases
- low power
- network on chip
- power dissipation
- ultra low power
- cmos technology
- power consumption
- wireless transmission
- high speed
- low cost
- single chip
- data transfer
- low latency
- routing algorithm
- digital signal processing
- data access
- multi processor
- network simulator
- image sensor
- data flow
- real time
- end to end
- response time