A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes.
Kiran K. GunnamGwan S. ChoiMark B. YearyPublished in: VLSI Design (2007)
Keyphrases
- low density parity check
- ldpc codes
- vlsi architecture
- decoding algorithm
- error correction
- message passing
- vlsi implementation
- channel coding
- low complexity
- real time
- image transmission
- distributed video coding
- low power
- rate allocation
- source coding
- non binary
- noise model
- belief propagation
- frequency domain
- computer simulation