A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch.
K. Wayne CurrentPublished in: ISMVL (1990)
Keyphrases
- low power
- logic circuits
- power dissipation
- flip flops
- power consumption
- high speed
- chip design
- low cost
- delay insensitive
- cmos technology
- power reduction
- logic synthesis
- single chip
- vlsi circuits
- threshold selection
- mixed signal
- nm technology
- digital signal processing
- circuit design
- analog vlsi
- image processing
- low voltage
- image sensor
- asynchronous circuits
- finite state machines
- real time