Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic.
Kalarikkal AbselLijo ManuelR. K. KavithaPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2013)
Keyphrases
- low power
- power consumption
- low cost
- logic circuits
- high speed
- power dissipation
- cmos technology
- delay insensitive
- flip flops
- vlsi circuits
- single chip
- high power
- digital signal processing
- vlsi architecture
- wireless transmission
- pattern recognition
- embedded systems
- low power consumption
- signal processor
- gate array
- efficient implementation
- parallel processing