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A High Efficiency 14-28 Gb/s Tunable Receiver Analog Front-End in 65 nm CMOS Technology.
Shunyu Li
Guangyong Chu
Kezhen Zhu
Pengfei Niu
Shixun Zhang
Guofeng Yang
Published in:
J. Circuits Syst. Comput. (2024)
Keyphrases
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high efficiency
cmos technology
mixed signal
low power
high speed
parallel processing
spl times
power consumption
low voltage
high accuracy
cmos image sensor
image sensor
silicon on insulator
low cost
power dissipation
single chip
image sequences
digital circuits