TSV array utilization in low-power 3D clock network design.
Xin ZhaoSung Kyu LimPublished in: ISLPED (2012)
Keyphrases
- network design
- low power
- power consumption
- high speed
- image sensor
- focal plane
- low cost
- single chip
- communication networks
- high power
- network design problem
- network architecture
- low power consumption
- logic circuits
- cmos technology
- wireless transmission
- power reduction
- vlsi circuits
- gate array
- vlsi architecture
- digital signal processing
- mixed signal
- resource utilization
- signal processing