A topology optimization method for low-power logic circuits with dual-threshold independent-gate FinFETs.
Haotian ZhuJianping HuHuishan YangYang XiongTingfeng YangPublished in: PATMOS (2017)
Keyphrases
- optimization method
- low power
- logic circuits
- cmos technology
- power consumption
- high speed
- low cost
- optimization algorithm
- optimization methods
- genetic algorithm
- evolutionary algorithm
- differential evolution
- nm technology
- particle swarm
- simulated annealing
- optimization procedure
- nelder mead simplex
- single chip
- gate array
- tunnel diode
- metaheuristic
- power dissipation
- vlsi circuits
- functional decomposition
- image sensor
- low power consumption
- cost function
- digital signal processing
- power reduction
- real time
- neural network
- mixed signal
- computer vision
- image processing
- wireless networks