Racetrack memory-based encoder/decoder for low-power interconnect architectures.
Suman DebLeibin NiHao YuAnupam ChattopadhyayPublished in: SAMOS (2016)
Keyphrases
- low power
- high speed
- video codec
- decoding process
- power reduction
- power dissipation
- distributed video coding
- low complexity
- error control
- power consumption
- wyner ziv
- low cost
- distributed source coding
- rate distortion
- single chip
- motion estimation
- interconnection networks
- bit rate
- video coding
- inter frame
- turbo codes
- transform domain
- logic circuits
- vlsi architecture
- temporal correlation
- rate allocation
- digital signal processing
- gate array
- low power consumption
- error resilience
- image sensor
- error correction
- signal processing
- motion compensation
- ldpc codes
- frame rate
- video quality
- motion compensated
- error concealment
- bit plane
- video coding standard
- power saving
- compressed video
- mixed signal
- image compression
- source coding