L3: An FPGA-based multilayer maze routing accelerator.
John A. NestorPublished in: Microprocess. Microsystems (2005)
Keyphrases
- field programmable gate array
- routing problem
- routing algorithm
- network topology
- routing protocol
- application specific
- hardware design
- routing decisions
- network topologies
- parallel implementation
- dynamic routing
- service requirements
- wireless ad hoc networks
- mobile ad hoc networks
- parallel computing
- hardware implementation
- ad hoc networks
- shortest path
- hardware software partitioning
- ant algorithm
- social networks
- inter domain
- traffic load
- hardware architecture
- computer vision