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An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz.
Montek Singh
José A. Tierno
Alexander V. Rylyakov
Sergey V. Rylov
Steven M. Nowick
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2010)
Keyphrases
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fir filters
vlsi implementation
asynchronous communication
circuit design
finite impulse response
frequency response
impulse response
digital filters
filter bank
linear algebra