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An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz.

Montek SinghJosé A. TiernoAlexander V. RylyakovSergey V. RylovSteven M. Nowick
Published in: IEEE Trans. Very Large Scale Integr. Syst. (2010)
Keyphrases
  • fir filters
  • vlsi implementation
  • asynchronous communication
  • circuit design
  • finite impulse response
  • frequency response
  • impulse response
  • digital filters
  • filter bank
  • linear algebra