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Latency-Guided On-Chip Bus-Network Design.
Milenko Drinic
Darko Kirovski
Seapahn Megerian
Miodrag Potkonjak
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2006)
Keyphrases
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network design
high speed
low latency
communication networks
heuristic solution
network design problem
network architecture
low cost
facility location
response time
prefetching
information systems
high density
data transfer
low power
distributed environment
supply chain
reverse logistics
metadata