Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture.
Avinash Karanth KodiAshwini SarathyAhmed LouriPublished in: ANCS (2007)
Keyphrases
- low power
- vlsi architecture
- cmos technology
- power dissipation
- network on chip
- power consumption
- low cost
- single chip
- communication channels
- high speed
- low power consumption
- mixed signal
- nm technology
- logic circuits
- digital signal processing
- real time
- design process
- packet switched
- gate array
- design methodology
- network simulator