A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA.
Libo ChangShengbing ZhangHuimin DuYue ChenShiyu WangPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2021)
Keyphrases
- systolic array
- parallel architecture
- object detection
- neural network
- digital signal
- hardware implementation
- shared memory
- reconfigurable architecture
- field programmable gate array
- memory management
- high end
- xilinx virtex
- fpga device
- low cost
- general purpose processors
- cell processor
- high speed
- fine grained
- parallel processing
- single chip
- distributed memory
- video processing
- computer vision
- reconfigurable hardware
- gate array
- data flow
- back propagation
- object categories
- artificial neural networks
- face detection
- parallel algorithm
- hardware architecture
- neural network model
- computing systems
- computation intensive
- general purpose
- neural network is trained
- level parallelism
- hardware design
- parallel programming
- pedestrian detection
- scene understanding
- efficient implementation
- message passing
- processing elements
- genetic algorithm
- multi class
- parallel implementation
- induction motor
- real time
- object recognition
- operating system
- highly parallel
- background subtraction
- image processing algorithms
- parallel computing
- object detectors
- embedded systems
- power reduction
- fine grain
- graphics processing units