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Multi Clock Flooded LDPC Decoding Architecture with Reduced Memory and Interconnect.
Oana Boncalo
Ioana Mot
Published in:
ISVLSI (2016)
Keyphrases
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high speed
ldpc codes
decoding algorithm
low density parity check
associative memory
random access
memory management
parallel architecture
processing elements
management system
memory requirements
memory access
clock frequency