Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system.
Hirokazu MorishitaKenta InakagataYasunori OsanaNaoyuki FujitaHideharu AmanoPublished in: SIGARCH Comput. Archit. News (2010)
Keyphrases
- hardware implementation
- parallel architecture
- hardware architectures
- fpga technology
- implementation issues
- real time
- hardware design
- fpga hardware
- pipeline architecture
- dedicated hardware
- fpga implementation
- software implementation
- hardware architecture
- design methodology
- low cost
- implementation details
- evaluation process
- evaluation model
- field programmable gate array
- gold standard
- efficient implementation
- signal processing
- high speed
- reconfigurable hardware
- search engine
- learning algorithm
- databases
- pipelined architecture
- database