Low Power BIST with Smoother and Scan-Chain Reorder .

Nan-Cheng Lai Sying-Jyan Wang Yu-Hsuan Fu

Published in: Asian Test Symposium (2004)

Keyphrases

low power
power consumption
high speed
low cost
single chip
wireless transmission
low power consumption
logic circuits
high power
vlsi architecture
digital signal processing
vlsi circuits
cmos technology
mixed signal
gate array
power reduction
signal processor
low voltage
delay insensitive
image sensor