A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC.
Kentaro YoshiokaAkira ShikataRyota SekimotoTadahiro KurodaHiroki IshikuroPublished in: ASP-DAC (2013)
Keyphrases
- low power
- analog to digital converter
- single chip
- low cost
- high speed
- power consumption
- mixed signal
- logic circuits
- high power
- digital signal processing
- low power consumption
- image sensor
- image reconstruction
- vlsi circuits
- power reduction
- wireless transmission
- signal processor
- image processing
- gate array
- ultra low power
- nm technology
- vlsi architecture
- hardware and software