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Ultra-low voltage drain-bulk connected MOS transistors in weak and moderate inversion.

Athanasios DimakosMatthias BucherRupendra Kumar SharmaIlias Chlis
Published in: ICECS (2012)
Keyphrases
  • low voltage
  • design considerations
  • power line
  • high speed
  • cmos technology
  • digital images
  • response time
  • peer to peer