Saving Power by Synthesizing Gated Clocks for Sequential Circuits.

Luca Benini Polly Siegel Giovanni De Micheli

Published in: IEEE Des. Test Comput. (1994)

Keyphrases

power dissipation
data sets
case study
power consumption
real time
neural network
digital circuits
power distribution
sequential search
delay insensitive
high speed
power management
asynchronous circuits
power reduction
chip design