A low power VLSI architecture of SOVA-based turbo-code decoder using scarce state transition scheme.
Yan WangChi-Ying TsuiRoger S. ChengPublished in: ISCAS (2000)
Keyphrases
- turbo codes
- vlsi architecture
- low power
- channel coding
- distributed video coding
- low complexity
- error correction
- low density parity check
- power consumption
- low cost
- high speed
- compressed images
- vlsi implementation
- wireless channels
- error propagation
- source coding
- forward error correction
- ldpc codes
- video codec
- error resilience
- image transmission
- packet loss
- video transmission
- rate allocation
- real time
- error resilient
- video streaming
- rate distortion
- video coding
- motion estimation