Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOS.
Kairang ChenMartin Nielsen-LönnAtila AlvandpourPublished in: NORCAS (2016)
Keyphrases
- analog to digital converter
- high speed
- power consumption
- synthetic aperture radar
- low power
- shift register
- sar images
- delay insensitive
- image sensor
- random access memory
- image reconstruction
- cmos image sensor
- duty cycle
- sea ice
- linear array
- data flow
- analog vlsi
- automatic target recognition
- sar imagery
- discussion forums
- low cost
- asynchronous communication
- real time
- online discussion