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On-chip evolution of combinational logic circuits using an improved genetic-simulated annealing algorithm.
Qianyi Shang
Lijun Chen
Peng Peng
Published in:
Concurr. Comput. Pract. Exp. (2020)
Keyphrases
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logic circuits
simulated annealing algorithm
low power
genetic algorithm
high speed
simulated annealing
power dissipation
low cost
functional decomposition
power consumption
search algorithm
logic synthesis
gate array
evolutionary algorithm
tunnel diode
mutation operator
hybrid algorithm
metaheuristic
real time