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A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.
Luca Benini
Alberto Bocca
Alberto Bonanno
Alberto Macii
Enrico Macii
Jean-Luc Nagel
Christian Piguet
Massimo Poncino
Published in:
J. Low Power Electron. (2010)
Keyphrases
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digital circuits
data flow
power consumption
database
model based diagnosis
finite state machines
formal verification
response time
design methodology
coarse grained