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A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs.
Sumit K. Mandal
Gokul Krishnan
Chaitali Chakrabarti
Jae-Sun Seo
Yu Cao
Ümit Y. Ogras
Published in:
IEEE J. Emerg. Sel. Topics Circuits Syst. (2020)
Keyphrases
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heterogeneous computing
compute intensive
reconfigurable architecture
multi processor
data transfer
memory usage
computing power
memory space
memory requirements
low cost
general purpose
prefetching
neural network
field programmable gate array
routing algorithm
memory management
network on chip
response time