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ASIC Implementation of Efficient 512-Neuron 256K-Synapses Digital Neuromorphic Processor with On-Chip Encoding in 22nmFDX.
Ahmed Zaky Ghonem
Eslam Yahya Tawfik
Published in:
ISCAS (2024)
Keyphrases
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circuit design
single chip
cmos image sensor
high speed
neural network
physical design
instruction set
low cost
efficient implementation
design methodology
computer architecture
functional verification
signal processing
application specific
memory management
level parallelism