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AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC.
Francesco Restuccia
Alessandro Biondi
Mauro Marinoni
Giorgiomaria Cicero
Giorgio C. Buttazzo
Published in:
DAC (2020)
Keyphrases
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high speed
real time
higher level
low cost
signal processing
low power
virtual machine
levels of abstraction
case study
high level
data processing
anomaly detection
operating system