A Low-Power Multiplier with Bypassing Logic and Operand Decomposition.
Ko-Chi KuoChi-Wen ChouPublished in: IMECS (2006)
Keyphrases
- power dissipation
- low power
- logic circuits
- power consumption
- high speed
- low cost
- delay insensitive
- cmos technology
- single chip
- digital signal processing
- high power
- vlsi circuits
- wireless transmission
- vlsi architecture
- real time
- gate array
- asynchronous circuits
- floating point
- mixed signal
- parallel processing
- energy dissipation
- digital circuits
- image sensor