Multi-thread VLIW processor architecture for HDTV decoding.
Hansoo KimWoo-Seung YangMyoung-Cheol ShinSeung-Jai MinSeong-Ok BaeIn-Cheol ParkPublished in: CICC (2000)
Keyphrases
- level parallelism
- instruction set
- data flow
- parallel architecture
- management system
- real time
- software architecture
- industry standard
- parallel processing
- multi processor
- neural network
- computation intensive
- processing elements
- systolic array
- multi core processors
- memory management
- hardware architecture
- design considerations
- image quality
- low cost