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Design of a phase alignment circuit for lock in amplifiers in 1.8V-0.18μm CMOS technology.
M. Yerena-Mora
Oscar J. Cinco-Izquierdo
María Teresa Sanz-Pascual
Belén Calvo López
A. Márquez
Published in:
ICECS (2019)
Keyphrases
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cmos technology
power dissipation
low power
power consumption
low voltage
circuit design
mixed signal
design process
spl times
case study
video sequences
high speed
parallel processing
digital circuits
single phase