A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
Hyun-Woo LeeWon-Joo YunYoung-Kyoung ChoiHyang-Hwa ChoiJong-Jin LeeKi-Han KimShin-Deok KangJi-Yeon YangJae-Suck KangHyeng-Ouk LeeDong-Uk LeeSujeong SimYoung-Ju KimWon-Jun ChoiKeun-Soo SongSang-Hoon ShinHyung-Wook MoonSeung-Wook KwackJung-Woo LeeNak-Kyu ParkKwan-Weon KimYoung-Jung ChoiJin-Hong AhnByong-Tae ChungPublished in: ISSCC (2009)
Keyphrases
- power supply
- single phase
- high power
- energy dissipation
- energy supply
- electrical power
- intelligent control
- power quality
- high frequency
- dynamic random access memory
- solar energy
- cmos technology
- decision making
- input output
- low voltage
- genetic algorithm
- rbf neural network
- power consumption
- power dissipation
- high speed
- fuzzy logic
- artificial neural networks
- image processing