Optimized VLSI Circuit Partitioning and Testing Using ACO and BIST Architectures.
M. R. EzilarasanD. PreethiMan-Fai LeungHangjun CheXiangguang DaiPublished in: ISNN (2024)
Keyphrases
- high speed
- ant colony optimization
- vlsi circuits
- test cases
- chip design
- metaheuristic
- gate array
- software testing
- power dissipation
- signal processing
- ant colonies
- electronic circuits
- ant colony optimization metaheuristic
- neural network
- analog vlsi
- partitioning algorithm
- single chip
- aco algorithm
- genetic algorithm ga
- optimization algorithm