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A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS.
Chang-Ming Lai
Meng-Hung Shen
Yi-Da Wu
Kai-Hsiang Huang
Po-Chiun Huang
Published in:
ISCAS (2011)
Keyphrases
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high speed
phase locked loop
high sensitivity
power consumption
low power
low cost
sensitivity analysis
image compression
low frequency
high voltage