An SoC combining a 132dB QVGA pixel array and a 32b DSP/MCU processor for vision applications.
Pierre-François RuediPascal HeimSteve GygerFrançois KaessClaude ArmRicardo CaseiroJean-Luc NagelSilvio TodeschiniPublished in: ISSCC (2009)
Keyphrases
- systolic array
- high speed
- low power
- focal plane
- image sensor
- low power consumption
- signal processing
- database
- digital signal processing
- single chip
- image processing
- computer vision
- parallel processing
- digital signal
- vision system
- parallel architecture
- digital signal processor
- charge coupled device
- real time
- input image
- intensity values
- random access memory
- computer architecture
- infrared