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On Testability of Differential Split-Level CMOS Circuits.

S. M. AzizW. A. J. Waller
Published in: VLSI Design (1994)
Keyphrases
  • high speed
  • analog vlsi
  • delay insensitive
  • vlsi circuits
  • circuit design
  • cmos technology
  • power consumption
  • levels of abstraction
  • database
  • real time
  • power dissipation