Hardware Synthesis of a Parallel JPEG Decoder from its Functional Specification.
John HawkinsAli E. AbdallahPublished in: DIPES (2004)
Keyphrases
- fpga implementation
- parallel hardware
- hardware implementation
- decoding process
- massively parallel
- computer architecture
- multi core processors
- low complexity
- low cost
- image compression
- parallel architectures
- processing elements
- field programmable gate array
- parallel processing
- image coding
- computer systems
- hardware architecture
- parallel computation
- compression algorithm
- parallel computing
- parallel programming
- discrete cosine transform
- parallel implementation
- low density parity check
- real time
- image processing
- jpeg xr
- joint source channel
- image transmission
- distributed video coding
- error detection
- bit plane
- compressed images
- jpeg compression
- processing units
- lossless compression
- computing systems
- embedded systems