Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers.
Thaddeus J. GabaraWilhelm C. FischerJohn HarringtonWilliam W. TroutmanPublished in: IEEE J. Solid State Circuits (1997)
Keyphrases
- analog vlsi
- delay insensitive
- circuit design
- high speed
- vlsi circuits
- cmos technology
- power consumption
- floating gate
- chip design
- low power
- random access memory
- real time
- focal plane
- power dissipation
- mixed signal
- low voltage
- asynchronous circuits
- power supply
- design considerations
- fault diagnosis
- infrared
- artificial neural networks
- image processing
- data sets